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R-Amtech International, Inc.
2101 112th Avenue NE
Suite 210
Bellevue, Washington 98004
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HiPEPTM is an ideal technology for high volume production of high performance, low cost chip-scale packages. CHIVTM 3D packaging, R-Amtech's sister technology to HiPEP, can be used for stacking multiple die for both high-density memories and mixed signal applications.
The CHIV technology is a state-of-the-art three-dimensional packaging technology for semiconductor and passive components that provides significant benefits for a wide range of applications. The CHIV technology allows the integration of active and passive components. Modules can be designed for the most complex analog, digital, or mixed signal applications.
The CHIV technology utilizes conventional assembly processes, such as thin-film deposition, common to semiconductor fabrication and assembly. CHIV has fewer manufacturing operations than other technologies and it does not use photolithography or multi-level printed circuit boards, all contributing to lower cost. The process can be integrated into an existing semiconductor facility without significant modification to facilities or additional capital equipment. Both non-recurring and recurring costs can be relatively low compared to the economic and performance benefits of the technology.
The significant reductions in the mass and volume provided by this CHIV technology make this an ideal packaging technology for applications where space and weight are of paramount importance.
CHIV is a highly reliable technology due to design features that shorten interconnections, remove heat, and use deposited instead of welded or soldered connections. The use of integral heat sinks in the CHIV construction allows the temperatures within the module to be kept very low and uniform throughout the module. This reduces the operating temperature of active devices, minimizes thermal stresses, and results in very reliable modules.
CHIV's ability to interconnect components in all three dimensions means interconnections can be kept as short as possible. This minimizes parasitic inductance and capacitance due to these interconnections as well as reducing the propagation delays between elements. Terminating resistors and decoupling capacitors can be integrated into the module in very close proximity to semiconductor devices. The overall result is exceptional performance for high-speed applications.
CHIV technology can also be used at cryogenic temperatures where the thin-film interconnects are more reliable than conventional techniques such as wire bonding.
R-Amtech owns the rights to five U.S. Patents that cover the CHIV three-dimensional chip stacking and HiPEP chip-scale packaging technologies.
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