R-Amtech International


		Overview
		Aerosol Generator
		CHIV
		HiPEP
		Mastic
		Pure 'N Clear

R-Amtech International, Inc.
2101 112th Avenue NE
Suite 210
Bellevue, Washington 98004

HiPEP^TM Features and Advantages

This table summarizes the major advantages of the HiPEP^TM technology:

Characteristic	Advantage
Wire bonds	None
Package Height	Approximately die height plus solder bumps
Solder Bumps	Formed on thin-film and not directly on die
Speed Capability	Very high (>10Ghz)
Decoupling Capacitors	Internal two pacakge and very close to die
Controlled Imepedance	Easy to implement
Termination Resistors	Easy to implement
Impedance Matching Components	Possible with thin-film components
Thermal Resistance	Low
Lead Connections	Anywhere on die
Reliability	High
Applications	Digital, analog and mixed-signal

The traditional competition for very high-density packaging has come from multi-chip modules (MCM) and 3D packaging technologies. More recently, chip-scale packages have become available where the package is almost the same size as the die. These CSP packages are becoming more popular as pin counts and IC sizes increase.

Multi-chip modules use bare die that are wire-bonded or flip-chipped to a multiplayer substrate, which is either an organic printed circuit board or ceramic. While MCMs have been used in many applications, the high costs associated with the technology and availability of known good die have prevented it becoming a mainstream packaging technology.

Most three-dimensional packaging applications have been in the memory area where the memory bus structures allow relatively easy interconnection in the third dimension. The high cost of three-dimensional packaging has prevented these technologies from becoming mainstream except for applications that demand the highest packaging densities.

HiPEP process has been extended to 3D packaging with R-Amtech's CHIV process. In this process multiple HiPEP devices are stacked and interconnected using thin-film interconnect techniques. CHIV technology differs from other 3D packaging technologies in that it is easily adapted to analog and mixed-signal applications in addition to memory applications.

For chip-scale packages the closest competition comes from Intel's Bumpless Buildup Layer Process (BBUL), which is also based on embedding ICs in a substrate and interconnecting them with thin-film interconnects. Other CSP processes such as Amkor's etCSP device are based on flip-chip and wire-bonding techniques and do not possess the superior high-speed and density advantages of HiPEP.

Technology	Competition	HiPEP Advantages
MCM	Flip-chip or wire bonded devices on a multiplayer substrate	Thin-film connections directly to IC with higher density interconnects Superior high-speed properties Better access to the back of the die for heat sinking
Three-Dimensional Packaging	Primarily in memory	Easily applied to both mixed-signal and memory systems. Superior high-speed Superior heat sink properties
Chip-Scale Packaging	Amkor etCSP, AMD FBGA packages, and Intel BBUL	Superior high-speed Superior heat sink properties Very low heights Package size very close to chip-size

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